Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. There are generally three sources of electrostatic discharge. One source is from an electrostatically charged human body, referred to as a human body model (HBM). Generally, transient currents with several amperes and potentials of 4 to 5 kV are created during the discharge, and in many cases can surpass the maximum current that a device can carry without producing damage to an IC device. Another source of ESD events is from metallic objects, often referred to as machine model (MM) events, where the potentials created during the transient are several hundred Volts, for example from about 200 to about 400 Volts. A third source is the discharge of the IC itself, which discharges to ground by current flowing out of the IC to ground, also referred to as the charged device model (CDM).
As IC devices decrease in size, the push for smaller dimension devices including metal interconnect lines has been the trend to achieve a higher device density. In addition, insulating dielectric layers have become thinner, leading to higher electrical field strengths for a given applied voltage. Both of these factors have the disadvantage of making an IC semiconductor device more susceptible to damage from ESD events.
Several approaches have been proposed to protect integrated circuits from ESD events. More common approaches include voltage clamping devices and bipolar transistors associated with an NMOS transistor, also referred to as a silicon controlled rectifier (SOR). The drain of the NMOS transistor is connected to an input/output signal source, for example a bonding pad, and the source of the NMOS transistor diffusion region is connected to ground. The SCR acts to trigger voltage clamping circuitry and discharges ESD voltages to ground after being triggered through the NMOS transistor. However, if the ESD voltage introduced into the circuit is above a certain potential, current passing through the gate oxide of the NMOS transistor or other portions of the integrated circuit can be damaged, including gate oxide dielectric breakdown, thereby obviating the protective ESD circuitry. The NMOS transistor resistance to dielectric breakdown may be adjusted to a certain degree by varying the dopant properties of the diffusion regions as well as the widths of the source and drain regions of the transistor. However, when bipolar NMOS transistors are operating under what is referred to as snapback conditions, the generation of current by the ESD transient voltage may cause circuitry failure, including gate oxide dielectric breakdown, where generated currents exceeding a critical value cause self-heating or runaway heating.
In particular, one problem with ESD protection circuits of the prior art, is that the current capacity limits are generally reached at unacceptably low transient voltages, especially in the MM ECD model, where transient voltages are on the order of 200 Volts to about 400 Volts. While ESD protection circuits including SCR circuits have been modified to increase a current carrying capacity, the metal routing of the circuit, including for example, input/output bonding pad to ground, contributes to constraints on current carrying limits by presenting an increased resistance to ground together with debiasing effects, where the potential over the metal routing pathway varies and produces areas of high potential, also referred to as “hot spots”.
There is therefore a need in the ESD circuit protection art to increase current carrying capacities of metal interconnect routing to improve the performance of ESD protection circuits thereby reducing gate breakdown events and improving the ESD circuit protection performance.
It is therefore an object of the invention to provide an apparatus and method for increasing current carrying capacities of metal interconnect routing to improve the performance of ESD protection circuits thereby reducing gate breakdown events and improving the ESD circuit protection performance while overcoming other shortcomings and limitations of the prior art.